Discussion:
USB 3.0 xhci questions
Ryo ONODERA
2014-08-10 13:44:24 UTC
Permalink
Hi,

I have read some xhci-related source code, and I have two questions.


(1) The definition of XHCI_HCS2_MAXSPBUF macro.
In src/sys/dev/usb/xhcireg.h, there is the following macro definition.

#define XHCI_HCS2_MAXSPBUF(x) (((x) >> 27) & 0x7F)

It seems that XHCI_HCS2_MAXSPBUF is used for reading Max Scratchpad Buffers.
Max Scratchpad Buffers are in 31:27 bit of HCSPARAMS2 in capability
register. 0x7F is 1111111(2). I feel it is too long to mask 31:27.
It would be 0x1F = 11111(2).


(2) I may not get USB Status (USBSTS).
In src/sys/dev/usb/xhci.c's xhci_intr1() function, USBSTS is read from
operational register, but my machine returns always 0x00000000.
The code in xhci_intr1() expects XHCI_STS_PCD flag is detcted.

The following is my modified source code snipet (enable device_printf).
I think "usbsts & XHCI_STS_PCD != 0" in this case, but always "== 0".
PCD means Port Change Detect, and port change is not detected.
I have dumped all PORTSC value, and there is no Current Connect Status (CCS)
and Connect Status Change (CSC) bits.

I have concluded that port change is not deteced on my machine.
What may be wrong?

int
xhci_intr1(struct xhci_softc * const sc)
{
uint32_t usbsts;
uint32_t iman;

usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts);
#if 0
if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) {
return 0;
}
#endif
xhci_op_write_4(sc, XHCI_USBSTS,
usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */
usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts);

iman = xhci_rt_read_4(sc, XHCI_IMAN(0));
device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman);
if ((iman & XHCI_IMAN_INTR_PEND) == 0) {
return 0;
}


And here is a part of dmesg.

xhci0 at pci0 dev 20 function 0: vendor 0x8086 product 0x8c31 (rev. 0x04)
xhci0: interrupting at ioapic0 pin 16
xhci_init
xhci0: xHCI version 1.0
xhci0: ac64 1 ctxsz 32
xhci0: xECP 8000
xhci0: ECR 8000: 02000802
xhci0: SP: 02000802 20425355 30010f01
xhci0: ECR 8020: 03000802
xhci0: SP: 03000802 20425355 10000610
xhci0: ECR 8040: 00000cc1
xhci0: ECR 8070: 0000ffc0
xhci0: ECR 846c: 00000001
xhci0: PAGESIZE 0x00000001
xhci0: sc_pgsz 0x00001000
xhci0: sc_maxslots 0x00000020
xhci0: sc_maxspbuf 16
xhci0: eventst: NORMAL_COMPLETION 000000013a6cbfc0 0xffff80023a25cfc0 1000
xhci0: dcbaa: NORMAL_COMPLETION 000000013a6cc000 0xffff80023a25d000 1000
xhci0: USBCMD 00000005
usb0 at xhci0: USB revision 2.0

xhci1 at pci3 dev 0 function 0: vendor 0x1912 product 0x0015 (rev. 0x02)
xhci1: interrupting at ioapic0 pin 17
xhci_init
xhci1: xHCI version 1.0
xhci1: ac64 1 ctxsz 64
xhci1: xECP 500
xhci1: ECR 500: 00000401
xhci1: ECR 510: 03000502
xhci1: SP: 03000502 20425355 00000201
xhci1: ECR 524: 02000702
xhci1: SP: 02000702 20425355 00000203
xhci1: ECR 540: 000004c0
xhci1: ECR 550: 0000000a
xhci1: PAGESIZE 0x00000001
xhci1: sc_pgsz 0x00001000
xhci1: sc_maxslots 0x00000020
xhci1: sc_maxspbuf 4
xhci1: eventst: NORMAL_COMPLETION 000000013a6cbf40 0xffff80023a25cf40 1000
xhci1: dcbaa: NORMAL_COMPLETION 000000013a84e000 0xffff80023a2e5000 1000
xhci1: USBCMD 00000005
usb1 at xhci1: USB revision 2.0

(USB 3.0 memory stick is inserted)
xhci_intr: xhci0
xhci0: xhci_intr1 USBSTS 00000000
xhci0: xhci_intr1 USBSTS 00000000
xhci0: xhci_intr1 IMAN0 00000002

Sadly, if my guess (1) was true, my MacBook Air' and
Lenovo ThinkStation E32's USB 3.0 does not work. No device is detected.

Thank you.

--
Ryo ONODERA // ***@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Taylor R Campbell
2014-08-10 13:59:57 UTC
Permalink
Date: Sun, 10 Aug 2014 22:44:24 +0900 (JST)
From: Ryo ONODERA <***@yk.rim.or.jp>

(1) The definition of XHCI_HCS2_MAXSPBUF macro.
In src/sys/dev/usb/xhcireg.h, there is the following macro definition.

#define XHCI_HCS2_MAXSPBUF(x) (((x) >> 27) & 0x7F)

It seems that XHCI_HCS2_MAXSPBUF is used for reading Max Scratchpad Buffers.
Max Scratchpad Buffers are in 31:27 bit of HCSPARAMS2 in capability
register. 0x7F is 1111111(2). I feel it is too long to mask 31:27.
It would be 0x1F = 11111(2).

Whatever the physical register specification is, please use __BITS and
__SHIFTOUT to describe it -- these is much easier to work with and
have fewer moving parts to get wrong than ands and shifts, and if you
ever need to assemble an hcs2 from its components you can use
__SHIFTIN with the same __BITS.

#define XHCI_HCS2_MAXSPBUF __BITS(31,27)

maxspbuf = __SHIFTOUT(hcs2, XHCI_HCS2_MAXSPBUF);
hcs2 = __SHIFTIN(maxspbuf, XHCI_HCS2_MAXSPBUF) | ...;
Ryo ONODERA
2014-08-12 15:55:34 UTC
Permalink
Hi,
Post by Taylor R Campbell
Date: Sun, 10 Aug 2014 22:44:24 +0900 (JST)
(1) The definition of XHCI_HCS2_MAXSPBUF macro.
In src/sys/dev/usb/xhcireg.h, there is the following macro definition.
#define XHCI_HCS2_MAXSPBUF(x) (((x) >> 27) & 0x7F)
It seems that XHCI_HCS2_MAXSPBUF is used for reading Max Scratchpad Buffers.
Max Scratchpad Buffers are in 31:27 bit of HCSPARAMS2 in capability
register. 0x7F is 1111111(2). I feel it is too long to mask 31:27.
It would be 0x1F = 11111(2).
Whatever the physical register specification is, please use __BITS and
__SHIFTOUT to describe it -- these is much easier to work with and
have fewer moving parts to get wrong than ands and shifts, and if you
ever need to assemble an hcs2 from its components you can use
__SHIFTIN with the same __BITS.
#define XHCI_HCS2_MAXSPBUF __BITS(31,27)
maxspbuf = __SHIFTOUT(hcs2, XHCI_HCS2_MAXSPBUF);
hcs2 = __SHIFTIN(maxspbuf, XHCI_HCS2_MAXSPBUF) | ...;
Thanks for your advice.

I have created attached patch.
With this patch, my machine does not work like before...

--
Ryo ONODERA // ***@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Takahiro HAYASHI
2014-08-11 08:58:12 UTC
Permalink
Hello,
Post by Ryo ONODERA
Sadly, if my guess (1) was true, my MacBook Air' and
Lenovo ThinkStation E32's USB 3.0 does not work. No device is detected.
Do these xHCIs work on other OS?
If yes, hardware seems good.
--
t-hash
Ryo ONODERA
2014-08-11 12:51:54 UTC
Permalink
Hi,
Post by Takahiro HAYASHI
Hello,
Post by Ryo ONODERA
Sadly, if my guess (1) was true, my MacBook Air' and
Lenovo ThinkStation E32's USB 3.0 does not work. No device is
detected.
Do these xHCIs work on other OS?
If yes, hardware seems good.
Arch Linux (archlinux-2014.08.01.iso; Linux 3.15.7) works fine
on both machines. SuperSpeed USB device is detected and attached to xhci.
Hardwares have no problem.

--
Ryo ONODERA // ***@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Takahiro HAYASHI
2014-08-11 17:14:43 UTC
Permalink
Hello,
Post by Ryo ONODERA
Post by Takahiro HAYASHI
Do these xHCIs work on other OS?
If yes, hardware seems good.
Arch Linux (archlinux-2014.08.01.iso; Linux 3.15.7) works fine
on both machines. SuperSpeed USB device is detected and attached to xhci.
Hardwares have no problem.
Thanks for checking.

I have no good idea to explain this.
It looks like xhci_intr is called even though
no interrupters trigger.

I have some questions.

1) Do you have PCI_INTR_FIXUP in your kernel config?
2) Is the port enabled -- has XHCI_PS_PED in PORTSC?

I think address of USBSTS is correct because
xhci_init returns normally and xhci is configured.


For comparison here is dmesg from my testbed:

xhci0 at pci5 dev 0 function 0: vendor 0x1033 product 0x0194 (rev. 0x04)
xhci0: interrupting at ioapic0 pin 21
xhci_init
xhci0: ac64 1 ctxsz 32
xhci0: xECP 500
xhci0: ECR 500: 00000401
xhci0: ECR 510: 03000402
xhci0: SP: 03000402 20425355 00000201
xhci0: ECR 520: 02000002
xhci0: SP: 02000002 20425355 00000203
xhci0: PAGESIZE 0x00000001
xhci0: sc_pgsz 0x00001000
xhci0: sc_maxslots 0x00000020
xhci0: sc_maxspbuf 0
xhci0: eventst: NORMAL_COMPLETION 0000000002f15fc0 0xffff800013028fc0 1000
xhci0: dcbaa: NORMAL_COMPLETION 0000000002f17000 0xffff800013029000 1000
xhci0: USBCMD 00000005
usb5 at xhci0: USB revision 2.0
usb5: WARNING: power management not supported

and i got:

xhci0: xhci_intr1 USBSTS 00000018
xhci0: xhci_intr1 USBSTS 00000000
xhci0: xhci_intr1 IMAN0 00000003
xhci0: xhci_intr1 IMAN0 00000002
xhci0: xhci_intr1 USBSTS 00000000
xhci0: port 1 status change
--
t-hash
Ryo ONODERA
2014-08-12 11:37:27 UTC
Permalink
Hi,
Post by Takahiro HAYASHI
Hello,
Post by Ryo ONODERA
Post by Takahiro HAYASHI
Do these xHCIs work on other OS?
If yes, hardware seems good.
Arch Linux (archlinux-2014.08.01.iso; Linux 3.15.7) works fine
on both machines. SuperSpeed USB device is detected and attached to xhci.
Hardwares have no problem.
Thanks for checking.
I have no good idea to explain this.
It looks like xhci_intr is called even though
no interrupters trigger.
I have some questions.
1) Do you have PCI_INTR_FIXUP in your kernel config?
I had no PCI_INTR_FIXUP in kernel config.
I have added PCI_INTR_FIXUP to my kernel config, and no effects.
Post by Takahiro HAYASHI
2) Is the port enabled -- has XHCI_PS_PED in PORTSC?
All PORTSC is 0x2a0.
It means port is disabled?

Thank you.
Post by Takahiro HAYASHI
I think address of USBSTS is correct because
xhci_init returns normally and xhci is configured.
xhci0 at pci5 dev 0 function 0: vendor 0x1033 product 0x0194
(rev. 0x04)
xhci0: interrupting at ioapic0 pin 21
xhci_init
xhci0: ac64 1 ctxsz 32
xhci0: xECP 500
xhci0: ECR 500: 00000401
xhci0: ECR 510: 03000402
xhci0: SP: 03000402 20425355 00000201
xhci0: ECR 520: 02000002
xhci0: SP: 02000002 20425355 00000203
xhci0: PAGESIZE 0x00000001
xhci0: sc_pgsz 0x00001000
xhci0: sc_maxslots 0x00000020
xhci0: sc_maxspbuf 0
xhci0: eventst: NORMAL_COMPLETION 0000000002f15fc0 0xffff800013028fc0 1000
xhci0: dcbaa: NORMAL_COMPLETION 0000000002f17000 0xffff800013029000 1000
xhci0: USBCMD 00000005
usb5 at xhci0: USB revision 2.0
usb5: WARNING: power management not supported
xhci0: xhci_intr1 USBSTS 00000018
xhci0: xhci_intr1 USBSTS 00000000
xhci0: xhci_intr1 IMAN0 00000003
xhci0: xhci_intr1 IMAN0 00000002
xhci0: xhci_intr1 USBSTS 00000000
xhci0: port 1 status change
--
t-hash
--
Ryo ONODERA // ***@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Takahiro HAYASHI
2014-08-12 12:49:35 UTC
Permalink
[snip]
Post by Ryo ONODERA
Post by Takahiro HAYASHI
I have some questions.
1) Do you have PCI_INTR_FIXUP in your kernel config?
I had no PCI_INTR_FIXUP in kernel config.
I have added PCI_INTR_FIXUP to my kernel config, and no effects.
hmm..
Post by Ryo ONODERA
Post by Takahiro HAYASHI
2) Is the port enabled -- has XHCI_PS_PED in PORTSC?
All PORTSC is 0x2a0.
It means port is disabled?
Yes, disabled.

xHCI 1.1 section 5.4.8 PORTSC reg says 0x2a0 means
XHCI_PS_CCS = 0: device is not connected
XHCI_PS_PED = 0: port disabled
XHCI_PS_PLS = 0x5: Link is in the RxDetect state
XHCI_PS_PP = 1: not power-off state

RxDetect is the state after port warm reset.
In this state controller is waiting for device.


- xHCI specification 1.1
http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
--
t-hash
Ryo ONODERA
2014-08-12 15:57:39 UTC
Permalink
Post by Takahiro HAYASHI
[snip]
Post by Ryo ONODERA
Post by Takahiro HAYASHI
I have some questions.
1) Do you have PCI_INTR_FIXUP in your kernel config?
I had no PCI_INTR_FIXUP in kernel config.
I have added PCI_INTR_FIXUP to my kernel config, and no effects.
hmm..
Post by Ryo ONODERA
Post by Takahiro HAYASHI
2) Is the port enabled -- has XHCI_PS_PED in PORTSC?
All PORTSC is 0x2a0.
It means port is disabled?
Yes, disabled.
xHCI 1.1 section 5.4.8 PORTSC reg says 0x2a0 means
XHCI_PS_CCS = 0: device is not connected
XHCI_PS_PED = 0: port disabled
XHCI_PS_PLS = 0x5: Link is in the RxDetect state
XHCI_PS_PP = 1: not power-off state
RxDetect is the state after port warm reset.
In this state controller is waiting for device.
- xHCI specification 1.1
http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
Hi,

Thanks for your explanation.
I read xhci spec already.
But I cannot find missing something for Intel xhci device...

--
Ryo ONODERA // ***@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Ryo ONODERA
2014-08-13 11:31:31 UTC
Permalink
Post by Ryo ONODERA
Post by Takahiro HAYASHI
[snip]
Post by Ryo ONODERA
Post by Takahiro HAYASHI
I have some questions.
1) Do you have PCI_INTR_FIXUP in your kernel config?
I had no PCI_INTR_FIXUP in kernel config.
I have added PCI_INTR_FIXUP to my kernel config, and no effects.
hmm..
Post by Ryo ONODERA
Post by Takahiro HAYASHI
2) Is the port enabled -- has XHCI_PS_PED in PORTSC?
All PORTSC is 0x2a0.
It means port is disabled?
Yes, disabled.
xHCI 1.1 section 5.4.8 PORTSC reg says 0x2a0 means
XHCI_PS_CCS = 0: device is not connected
XHCI_PS_PED = 0: port disabled
XHCI_PS_PLS = 0x5: Link is in the RxDetect state
XHCI_PS_PP = 1: not power-off state
RxDetect is the state after port warm reset.
In this state controller is waiting for device.
- xHCI specification 1.1
http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
Hi,
Thanks for your explanation.
I read xhci spec already.
But I cannot find missing something for Intel xhci device...
Hi,

I have found xHC halting is done before resetting, and Linux and edk2
confirm whether xHC is really halted.
I have added similar code to NetBSD's xhci.c like following.

And I have gotten

xhci0: init failed, error=5

error.

Index: xhci.c
===================================================================
RCS file: /cvsroot/src/sys/dev/usb/xhci.c,v
retrieving revision 1.26
diff -u -r1.26 xhci.c
--- xhci.c 12 Aug 2014 13:50:42 -0000 1.26
+++ xhci.c 13 Aug 2014 11:26:39 -0000
@@ -682,7 +682,14 @@

usbcmd = 0;
xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
- usb_delay_ms(&sc->sc_bus, 1);
+ for (i = 0; i < 100; i++) {
+ usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
+ if ((usbsts & XHCI_STS_HCH) == 0)
+ break;
+ usb_delay_ms(&sc->sc_bus, 1);
+ }
+ if (i >= 100)
+ return EIO;

usbcmd = XHCI_CMD_HCRST;
xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);

--
Ryo ONODERA // ***@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Ryo ONODERA
2014-08-13 13:57:16 UTC
Permalink
Post by Ryo ONODERA
Post by Ryo ONODERA
Post by Takahiro HAYASHI
[snip]
Post by Ryo ONODERA
Post by Takahiro HAYASHI
I have some questions.
1) Do you have PCI_INTR_FIXUP in your kernel config?
I had no PCI_INTR_FIXUP in kernel config.
I have added PCI_INTR_FIXUP to my kernel config, and no effects.
hmm..
Post by Ryo ONODERA
Post by Takahiro HAYASHI
2) Is the port enabled -- has XHCI_PS_PED in PORTSC?
All PORTSC is 0x2a0.
It means port is disabled?
Yes, disabled.
xHCI 1.1 section 5.4.8 PORTSC reg says 0x2a0 means
XHCI_PS_CCS = 0: device is not connected
XHCI_PS_PED = 0: port disabled
XHCI_PS_PLS = 0x5: Link is in the RxDetect state
XHCI_PS_PP = 1: not power-off state
RxDetect is the state after port warm reset.
In this state controller is waiting for device.
- xHCI specification 1.1
http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
Hi,
Thanks for your explanation.
I read xhci spec already.
But I cannot find missing something for Intel xhci device...
Hi,
I have found xHC halting is done before resetting, and Linux and edk2
confirm whether xHC is really halted.
I have added similar code to NetBSD's xhci.c like following.
And I have gotten
xhci0: init failed, error=5
error.
Index: xhci.c
===================================================================
RCS file: /cvsroot/src/sys/dev/usb/xhci.c,v
retrieving revision 1.26
diff -u -r1.26 xhci.c
--- xhci.c 12 Aug 2014 13:50:42 -0000 1.26
+++ xhci.c 13 Aug 2014 11:26:39 -0000
@@ -682,7 +682,14 @@
usbcmd = 0;
xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
- usb_delay_ms(&sc->sc_bus, 1);
+ for (i = 0; i < 100; i++) {
+ usbsts = xhci_op_read_4(sc, XHCI_USBSTS);
+ if ((usbsts & XHCI_STS_HCH) == 0)
+ break;
+ usb_delay_ms(&sc->sc_bus, 1);
+ }
+ if (i >= 100)
+ return EIO;
usbcmd = XHCI_CMD_HCRST;
xhci_op_write_4(sc, XHCI_USBCMD, usbcmd);
Oops.
(usbsts & XHCI_STS_HCH) == 0 should be 1.
It is my misunderstanding.

Sorry.

--
Ryo ONODERA // ***@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Ryo ONODERA
2014-08-17 12:52:31 UTC
Permalink
Hi,
Post by Ryo ONODERA
Post by Takahiro HAYASHI
[snip]
Post by Ryo ONODERA
Post by Takahiro HAYASHI
I have some questions.
1) Do you have PCI_INTR_FIXUP in your kernel config?
I had no PCI_INTR_FIXUP in kernel config.
I have added PCI_INTR_FIXUP to my kernel config, and no effects.
hmm..
Post by Ryo ONODERA
Post by Takahiro HAYASHI
2) Is the port enabled -- has XHCI_PS_PED in PORTSC?
All PORTSC is 0x2a0.
It means port is disabled?
Yes, disabled.
xHCI 1.1 section 5.4.8 PORTSC reg says 0x2a0 means
XHCI_PS_CCS = 0: device is not connected
XHCI_PS_PED = 0: port disabled
XHCI_PS_PLS = 0x5: Link is in the RxDetect state
XHCI_PS_PP = 1: not power-off state
RxDetect is the state after port warm reset.
In this state controller is waiting for device.
- xHCI specification 1.1
http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
Hi,
Thanks for your explanation.
I read xhci spec already.
But I cannot find missing something for Intel xhci device...
I have found the missing one, and post to my PR.
http://gnats.netbsd.org/49076

It works for Lynx Point xhci,
but does not work fine for Lynx Point-LP xhci.

If you have Lynx Point-LP machine, could you test my patch in
PR kern/49076?
My Lynx Point-LP machine is MacBook Air early 2014 11-inch.
I would like to know the status on non-Apple Lynx Point-LP machine especially.

Thank you.

--
Ryo ONODERA // ***@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Ryo ONODERA
2014-08-17 12:53:49 UTC
Permalink
Post by Ryo ONODERA
Hi,
Post by Ryo ONODERA
Post by Takahiro HAYASHI
[snip]
Post by Ryo ONODERA
Post by Takahiro HAYASHI
I have some questions.
1) Do you have PCI_INTR_FIXUP in your kernel config?
I had no PCI_INTR_FIXUP in kernel config.
I have added PCI_INTR_FIXUP to my kernel config, and no effects.
hmm..
Post by Ryo ONODERA
Post by Takahiro HAYASHI
2) Is the port enabled -- has XHCI_PS_PED in PORTSC?
All PORTSC is 0x2a0.
It means port is disabled?
Yes, disabled.
xHCI 1.1 section 5.4.8 PORTSC reg says 0x2a0 means
XHCI_PS_CCS = 0: device is not connected
XHCI_PS_PED = 0: port disabled
XHCI_PS_PLS = 0x5: Link is in the RxDetect state
XHCI_PS_PP = 1: not power-off state
RxDetect is the state after port warm reset.
In this state controller is waiting for device.
- xHCI specification 1.1
http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
Hi,
Thanks for your explanation.
I read xhci spec already.
But I cannot find missing something for Intel xhci device...
I have found the missing one, and post to my PR.
http://gnats.netbsd.org/49076
It works for Lynx Point xhci,
but does not work fine for Lynx Point-LP xhci.
If you have Lynx Point-LP machine, could you test my patch in
PR kern/49076?
My Lynx Point-LP machine is MacBook Air early 2014 11-inch.
I would like to know the status on non-Apple Lynx Point-LP machine especially.
Lynx Point-LP has vendor ID = 0x8086/product ID = 0x9c31.

Thank you.

--
Ryo ONODERA // ***@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Ryo ONODERA
2014-08-13 22:20:23 UTC
Permalink
Hi,
Post by Takahiro HAYASHI
xhci0 at pci5 dev 0 function 0: vendor 0x1033 product 0x0194
(rev. 0x04)
xhci0: interrupting at ioapic0 pin 21
xhci_init
xhci0: ac64 1 ctxsz 32
xhci0: xECP 500
xhci0: ECR 500: 00000401
xhci0: ECR 510: 03000402
xhci0: SP: 03000402 20425355 00000201
xhci0: ECR 520: 02000002
xhci0: SP: 02000002 20425355 00000203
xhci0: PAGESIZE 0x00000001
xhci0: sc_pgsz 0x00001000
xhci0: sc_maxslots 0x00000020
xhci0: sc_maxspbuf 0
xhci0: eventst: NORMAL_COMPLETION 0000000002f15fc0 0xffff800013028fc0 1000
xhci0: dcbaa: NORMAL_COMPLETION 0000000002f17000 0xffff800013029000 1000
xhci0: USBCMD 00000005
usb5 at xhci0: USB revision 2.0
usb5: WARNING: power management not supported
xhci0: xhci_intr1 USBSTS 00000018
xhci0: xhci_intr1 USBSTS 00000000
xhci0: xhci_intr1 IMAN0 00000003
xhci0: xhci_intr1 IMAN0 00000002
xhci0: xhci_intr1 USBSTS 00000000
xhci0: port 1 status change
On my machine, xhci_handle_event() is not invoked
when USB memory stick is plugged.
How about on your machine?

Thank you.

--
Ryo ONODERA // ***@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Takahiro HAYASHI
2014-08-13 23:18:18 UTC
Permalink
Post by Ryo ONODERA
Hi,
Post by Takahiro HAYASHI
xhci0 at pci5 dev 0 function 0: vendor 0x1033 product 0x0194
(rev. 0x04)
xhci0: interrupting at ioapic0 pin 21
xhci_init
xhci0: ac64 1 ctxsz 32
xhci0: xECP 500
xhci0: ECR 500: 00000401
xhci0: ECR 510: 03000402
xhci0: SP: 03000402 20425355 00000201
xhci0: ECR 520: 02000002
xhci0: SP: 02000002 20425355 00000203
xhci0: PAGESIZE 0x00000001
xhci0: sc_pgsz 0x00001000
xhci0: sc_maxslots 0x00000020
xhci0: sc_maxspbuf 0
xhci0: eventst: NORMAL_COMPLETION 0000000002f15fc0 0xffff800013028fc0 1000
xhci0: dcbaa: NORMAL_COMPLETION 0000000002f17000 0xffff800013029000 1000
xhci0: USBCMD 00000005
usb5 at xhci0: USB revision 2.0
usb5: WARNING: power management not supported
xhci0: xhci_intr1 USBSTS 00000018
xhci0: xhci_intr1 USBSTS 00000000
xhci0: xhci_intr1 IMAN0 00000003
xhci0: xhci_intr1 IMAN0 00000002
xhci0: xhci_intr1 USBSTS 00000000
xhci0: port 1 status change
On my machine, xhci_handle_event() is not invoked
when USB memory stick is plugged.
How about on your machine?
It is called in my case.

xhci_intr: xhci0
xhci0: xhci_intr1 USBSTS 00000018
xhci0: xhci_intr1 USBSTS 00000000
xhci0: xhci_intr1 IMAN0 00000003
xhci0: xhci_intr1 IMAN0 00000002
xhci0: xhci_intr1 USBSTS 00000000
xhci_softintr: xhci0
xhci_handle_event: xhci0
xhci0: port 1 status change
xhci_softintr: xhci0 ends
--
t-hash
Ryo ONODERA
2014-08-14 12:11:56 UTC
Permalink
Post by Takahiro HAYASHI
Post by Ryo ONODERA
Hi,
Post by Takahiro HAYASHI
xhci0 at pci5 dev 0 function 0: vendor 0x1033 product 0x0194
(rev. 0x04)
xhci0: interrupting at ioapic0 pin 21
xhci_init
xhci0: ac64 1 ctxsz 32
xhci0: xECP 500
xhci0: ECR 500: 00000401
xhci0: ECR 510: 03000402
xhci0: SP: 03000402 20425355 00000201
xhci0: ECR 520: 02000002
xhci0: SP: 02000002 20425355 00000203
xhci0: PAGESIZE 0x00000001
xhci0: sc_pgsz 0x00001000
xhci0: sc_maxslots 0x00000020
xhci0: sc_maxspbuf 0
xhci0: eventst: NORMAL_COMPLETION 0000000002f15fc0 0xffff800013028fc0 1000
xhci0: dcbaa: NORMAL_COMPLETION 0000000002f17000 0xffff800013029000 1000
xhci0: USBCMD 00000005
usb5 at xhci0: USB revision 2.0
usb5: WARNING: power management not supported
xhci0: xhci_intr1 USBSTS 00000018
xhci0: xhci_intr1 USBSTS 00000000
xhci0: xhci_intr1 IMAN0 00000003
xhci0: xhci_intr1 IMAN0 00000002
xhci0: xhci_intr1 USBSTS 00000000
xhci0: port 1 status change
On my machine, xhci_handle_event() is not invoked
when USB memory stick is plugged.
How about on your machine?
It is called in my case.
xhci_intr: xhci0
xhci0: xhci_intr1 USBSTS 00000018
xhci0: xhci_intr1 USBSTS 00000000
xhci0: xhci_intr1 IMAN0 00000003
xhci0: xhci_intr1 IMAN0 00000002
xhci0: xhci_intr1 USBSTS 00000000
xhci_softintr: xhci0
xhci_handle_event: xhci0
xhci0: port 1 status change
xhci_softintr: xhci0 ends
Thank you very much.

--
Ryo ONODERA // ***@yk.rim.or.jp
PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
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